The present invention relates to a technique of semiconductor integrated circuit (device) and particularly to the technique which may be effectively applied to the semiconductor integrated circuit device including a bipolar device and a MISFET (Metal Insulator Semiconductor Field Effect Transistor) formed on one chip.
The semiconductor integrated circuit device is formed of various circuits and introduces a so-called Bi-CMOS circuit combining a bipolar transistor which assures high-speed operation property and a complementary MISFET which assures low power consumption.
Particularly, development of communication technology requires a semiconductor integrated circuit which ensures high-speed operation rate for wider frequency range.
For example, a CDR (Clocked Data Recovery) circuit for processing a high-speed signal is described in the ISSCC 2000 Digest of Technical Papers (Feb. 7, 2000) p. 57. As illustrated in FIG. 3.4.1 of this reference, a signal is outputted by synchronizing a high-speed input signal (Data input) with the clock signal generated by a VOC (Voltage-controlled Oscillator) circuit.
Moreover, the Japanese Unexamined Patent Publication No. Hei 6(1994)-237160 discloses the technique related to a multiplexer using Bi-CMOS, a logical gate, and an adder.
The inventors of the present invention have continued research and development of semiconductor integrated circuit device for processing a high-speed signal and particularly for IC (Integrated Circuit) for optical communication.
For example, an IC for optical communication in 10 Gbps (b/s) utilizes a bipolar ECL (Emitter-Coupled Logic) introducing a bipolar transistor for high-speed process of 10 Gbps signal.
However, this bipolar ECL circuit consumes a large amount of electrical power. Moreover, since scale of circuit becomes large as functions of IC are further sophisticated, power consumption of chip reaches the order of several watts.
As a result, such power consumption is a factor of rise in manufacturing cost because a type of package is restricted in order to assure good heat radiation characteristic of IC.
Accordingly, in view of attaining low power consumption, it is proposed that a MISFET is also used to process a low frequency signal with a complementary MISFET circuit.
For example, a PD (Phase Detector) circuit, a selector circuit, a VCO circuit and a DIV/64 circuit in the CDR circuit of ISSCC 2000 are respectively formed of bipolar circuit (BIPOLAR) to process a high-speed signal. Meanwhile, a PFD (Phase Frequency Detector) circuit and a Lock Detector circuit for processing the signal after the signal is frequency-divided to {fraction (1/64)} with the DIV/64 are respectively formed of CMOS of low power consumption.
However, even in this CDR circuit, since a circuit formed of CMOS is limited only to the circuit provided after the signal is frequency-divided to {fraction (1/64)} in the DIV/64, the effect of low power consumption is also restricted.
Therefore, an object of the present invention is to realize low power consumption of a semiconductor integrated circuit device, particularly of a device including a Bi-CMOS circuit.
Moreover, it is also an object of the present invention to improve the characteristics thereof such as improvement in the processing rate of the same device.
The aforementioned and the other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings thereof.
The typical profiles disclosed by the present invention will be briefly described as follows.
(1) The semiconductor integrated circuit device of the present invention is a semiconductor integrated circuit device comprising a bipolar device and a MISFET device, further including (a) a first circuit formed of a bipolar device, the first circuit receiving a first signal of a first frequency and outputting a second signal of a second frequency which is lower than the first frequency, (b) a level conversion circuit for converting level and amplitude of signal, the level conversion circuit receiving the second signal and outputting a third signal of the second frequency responding to the second signal, and (c) a second circuit comprised of a MISFET device, the second circuit receiving the third signal and outputting a fourth signal of a third frequency which is lower than the second frequency.
(2) The semiconductor integrated circuit device of the present invention is a semiconductor integrated circuit device comprising a bipolar device and a MISFET device further including (a) a first circuit comprised of a MISFET device, the first circuit receiving a first signal of a first frequency and outputting a second signal of a second frequency which is higher than the first frequency, (b) a level conversion circuit for converting level and amplitude of signal, the level conversion circuit receiving the second signal and outputting a third signal of the second frequency responding to the second signal, and (c) a second circuit comprised of a bipolar device, the second circuit receiving the third signal and outputting a fourth signal of the third frequency which is higher than the second frequency.